Partcl is ending the hardware lottery.
We are developing the next generation of chip design automation tools with a focus on performance, scalability and productivity. We envision a future where hardware engineers benefit from advances in AI and believe the first place to start is with advanced optimization tools.
What you will do:
• Help us design and verify digital logic using ML-assisted EDA workflows.
• You'll work across RTL, SPICE, and PDK layers to push real blocks through both open-source and proprietary toolchains.
• Write and verify RTL (Verilog/SystemVerilog) with LLM-assisted automation.
• Run synthesis, simulation, and timing analysis in open + closed EDA flows.
• Simulate SPICE netlists and debug transistor-level behavior. Script automation in Python/C++ to connect design stages.
Requirements:
• Strong RTL design and verification background.
• Familiar with SPICE simulation and PDK fundamentals.
• Experience with Yosys/OpenROAD or commercial EDA tools.
• Hands-on, fast-moving, results-focused.
