At a glance
Own physical implementation, tooling, and methodology for next-generation AI accelerator silicon, optimizing power, performance, and area from floorplan through final signoff.
Summarized by AI from the original posting
What you'll do
- Develop, build, and own tools, flows, and methodologies for physical implementation
- Own physical implementation of floorplan blocks from floorplanning through final signoff
- Collaborate with RTL designers on optimal block implementation
- Analyze and optimize timing, power, and area trade-offs
- Work with EDA vendors and ASIC partners
Requirements
- 01Demonstrated success taping out complex silicon designs
- 02Hands-on experience with block physical implementation and PPA convergence
- 03Strong coding experience with Python, Bazel, and TCL
- 04Strong experience building physical design tools, flows, and methodologies
- 05Deep understanding of microarchitecture, RTL design, physical design, circuit design, physical verification, and timing closure
- 06Familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC, and power estimation
Skills
Full description
About the Team
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.
About the Role
We are seeking a highly skilled Physical Design Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators.
You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon’s performance and cost efficiency, as well as the team’s execution velocity and quality.
In this role, you will:
Develop, build and own tools, flows and methodologies for physical implementation
Own physical implementation of floorplan blocks from floorplanning to final signoff
Collaborate with RTL designers to drive optimal block implementation solutions
Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners
Qualifications:
BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
Demonstrated success in taping out complex silicon designs
Hands-on experience with block physical implementation and PPA convergence
Strong coding experience with python, bazel, TCL
Strong experience building physical design tools, flows and methodologies
Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure.
Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation
Bonus:
Experience with AI or HPC-focused chips
Experience with optimizing PPA for high performance compute cores
Hands-on experience with top-level design methodologies
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.
About OpenAI
OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.
We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.
For additional information, please see OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement.
Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.
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At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.
Compensation: $266K - $445K